Today, we are in the internet-of-things (IoT) era – an era of sensors and components connected across a high speed communication infrastructure with analysis by massive data center “clouds”. The building blocks are systems-on-chip (SoC) integrated with several diverse IP modules.  Analog and mixed-signal (AMS) circuits form many of the critical components of SoCs that push the boundaries of high bandwidth and low power. AMS circuits, such as phase-locked loops, sensors, amplifiers, wired and wireless interfaces are often embedded in a chip with limited controllability to access them.  

The demand for high performance, high bandwidth and low power has resulted in AMS designs operating at their margins. The unimaginable levels of integration has come at the cost of increased manufacturing process variations, vulnerability to defects, and accelerated device aging. In this scenario, verifying and validating AMS circuits, which are particularly sensitive to variations and electrical noise, in both pre-silicon and post-silicon phases, has become a great challenge.  Effective diagnosis to improve AMS yield, and manufacturing test methods to detect catastrophic faults and unexpected process excursions that have contributed to increased AMS-related customer returns are a necessity.  Further, sensitive AMS circuits such as those used in health and automotive products need to have a high degree of in-field reliability requiring fault tolerance and adaptive operation.  Since most AMS circuits are often the gateways to a SoC, ensuring their secure design is of vital importance to prevent compromising the security of the chip. These quality objectives should be met under market requirements of aggressively low product cost and product cycle time.  

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems.  

Keynote, Thursday, Oct 8, 4:30PM PST
Leading Edge Mixed Signal IP Solutions – Trends, Challenges and Opportunities
Srinivasan Rajappa
Senior Director, Mixed-Signal IP Solutions Development Group
Intel Corporation, USA

Keynote, Friday, Oct 9, 8:00AM PST
Avoiding The Dark Side Of The Cloud Using Secure And Reliable IoT Devices
Navraj Nandra
Senior Director, Marketing, Analog/Mixed-Signal IP
Synopsys, USA

Embedded tutorial, Thursday, Oct 8, 5:30PM PST
On-Chip Structures for Test and Measurement of High-Speed Analog Circuits
Professor Jacob Abraham
University of Texas, Austin, USA

Panel, Friday, Oct 9, 1:00PM PST
Analog IPs in a commoditized and fragmented market: challenge or opportunity?
Moderated by Professor Mani Soma
University of Washington, USA

Registration is now open. For details on registration, venue, and travel, please visit the International Test Conference registration site http://www.itctestweek.org/register. Though the ITC registration site is used, TVHSAC’15 workshop registration does not require ITC registration. 

For information contact:

Suriya Natarajan - suriyaprakash.natarajan@intel.com

Manuel Barragan - manuel.barragan@imag.fr

General Chair

• Suriya Natarajan, Intel

Vice General Chair

• Yervant Zorian, Synopsys

Finance Chair

• Chen-Huan Chiang, Alcatel-Lucent

Publicity Chairs

• Yiorgos Makris, UT Dallas 
• Ke Huang, SDSU

Program Chair

• Manuel J. Barragan, TIMA

Program Committee

• Jacob Abraham, UT Austin
• Serge Bernard, LIRMM
• Ahcène Bouncer, U. Brest
• Kenneth Butler, TI
• John Carulli, Global Foundries
• Abhijit Chatterjee, Georgia Tech
• Jerzy Dabrowsky, Linkoping U.
• Emeric De Foucauld, CEA-LETI
• Ke Huang, SDSU
• Jaeha Kim, Seoul National U.
• Gildas Léger, IMSE-CNM
• Xin Li, CMU
• Amit Majumdar, Xilinx
• Yiorgos Makris, UT Dallas
• Srinivas Modekurty, Intel 
• Sule Ozev, ASU
• Arijit Raychowdhury, Georgia Tech
• Gordon Roberts, McGill U.
• Saghir Shaikh, Broadcom
• C.-J. Richard Shi, U. Washington
• Mustapha Slamani, GlobalFoundries
• Mani Soma, U. Washington
• Haralampos Stratigopoulos, LIP6
• Stephen Sunter, Mentor Graphics
• Shobha Vasudevan, U. Illinois UC
• Amir Zjajo, TU Delft

The 4th IEEE International Workshop on Test and Validation of High Speed Analog Circuits is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).